Qualification:
Students passing out in 2023 and Pursuing Bachelor / Master degree in Electronics Engineering /Micro Electronics/VLSI.
Ability to manage multiple tasks and work toward long-term goals.
Solid understanding of engineering fundamentals and technical problem-solving skills.
Experience in establishing and sustaining strong relationships with the extended team.
Excellent communication skills (verbal and written).
Knowledge in Hardware design, the test/verification environment is designed using an object-oriented framework designed in using UVM so you will use knowledge from your programming courses that include advance data structures, algorithms, and design patterns as well as languages such as SystemVerilog HDL / C / C++ / Python
You will aid in the architecture of the test environments which include developing constrained random stimulus generators, automated response checkers, and advanced configuration and programming API components using UVM.
Some of these components are reused across the entire phase of the project from module, chip and system level verification on Linux based Verilog simulators.
Problem solving skills and out-of-the-box thinking to create area and power efficient hardware designs as well as reusable UVM classes for the verification and simulation environments.
Physical Implementation of blocks, clock trees, Static Timing Analysis, DFT, Logic Equivalence Checks are part of the Physical Design specialist profile.
Writing thorough and detailed specifications and test plans as well as oral descriptions will enable your ideas and concepts to be reviewed and accepted by other team members.
Compnay | Cisco |
Role | Asic engineer |
Salary | not discloased |
Batch | 2023/2024 |
Qualification | Bachelors|Master degree |
Link | https://jobs.cisco.com/jobs/ProjectDetail/ASIC-Engineer-New-Grad-India-UHR/1376727 |
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